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京东 11.11 红包
genus synthesis tool_ power report | area report | schematic view
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TCL file for synthesis in genus_ design compiler
cadance工具进行 Logical Equivalence Check (LEC)
Analog Mixed Signal IC Design LEF File Generation using Cadence Abstract Tool Tu
SOC - Power - Advanced SOC Design 2024
Low Power Design - Dynamic Power Reduction - Advanced SOC Design 2024
Low Power Design - Power Basics : Advanced SOC Design 2024
gate level simulation in Xcelium
Creating a NAND Gate Schematic Step by Step Tutorial
Low Power Design - Static Power Reduction - Advanced SOC Design 2024
part 30 _Quartus_Synthesis综合
Advanced Verification - Low power UPF Advanced SOC Design
【DDR4】part 4 timings分析 tRAS, tRP, tRTP和tRC
低功耗设计及UPF文件详细介绍与power_report
AXI Bus Introduction
Introduction to SCAPS 1D software
Synopsys IC Compiler II Flow Introduction
#2 _ Verilog Review
Formality 使用及等价性检验
UVM Register Layer介绍
Clocking JESD204B⧸C systems
Writing SV UVM Testbench 03 - Testbench with Classes
JESD204 - Common Pitfalls and Traps
Advanced Verification_ Simulation Coverage - 以APB为例讲解覆盖率
SerDes Part 9 - Interfaces
SOC - IO Part I - Advanced SOC Design
SerDes Pert 6 - Sounds good!
Advanced STA - OCV/AOCV/POCV/AWP Advanced SOC Design 2024
Chip Design Flow Part II - Backend flow - Advanced SOC Design 2024
SerDes part 2_ The Signaling Quagmire
Verilog Tutorial :ADC AD7819 01
Writing SV UVM Testbench 04 - Enabling UVM _ Hello World in UVM
SOC - Reset - Advanced SOC Design 2024
SOC Clock Part I - Advanced SOC Design 2024
clock skew
UVM Verification Component介绍【动态展示】
UVM【Sequence】【Sequencer】【Driver】和【DUT】之间的握手
Advanced STA - Special Circuit Analysis - Advanced SOC Design 2024
ASOC NTU Final Project - Style Filter
SCAPS 1D tutorial_ Doping_Carrier Concentration- Where and How_
Advanced STA - Path-based Analysis - Advanced SOC Design 2024