SC3.High.Precision.and.Low.Power.ADCs
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3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy fro
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SC4.Emerging.Data.Converter.Concepts
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SC2.Ultra.High.Data.Rate.ADCs.and.DACs.Architectures.and.Implementations
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3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm°C from -20
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F2.Sensor.Interface.Analog.and.Mixed.Signal.Circuits.for.Miniaturized.IoT.Device
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SC1.Introduction.to.ADCs.DACs.Metrics.Topologies.Trade.Space.and.Applications
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3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BWPower Scalable Sensor Interface with a
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3.2 A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccura
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ESSCIRC 2024 Circuit Insights 4-Data Converters
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3.5 A 4mW 45pT√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Ca
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3.6 An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5d
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3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC U
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3.10 A 0.690.58-PEF 1.6nW24nW Capacitively Coupled Chopper Instrumentation Ampli
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3.8 A 0.65V 900μm2 BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -2
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9.2 A 2.08mW 64.4dB SNDR 400MSs 12b Pipelined-SAR ADC using Mismatch and PVT Var
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7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
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A 4.8GSs 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing
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9.4 A 182.3dB FoMs 50MSs Pipelined-SAR ADC using Cascode Capacitively Degenerate
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A 12GSs 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration
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模拟集成电路设计8-运算放大器的设计
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3.3 A 0.5V 6.14µW Trimming-Free Single-XO Dual-Output Frequency Reference with [
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7.4 A A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scorin
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10.6 A 10GHz FMCW Modulator Achieving 680MHzμs Chirp Slope and 150kHz rms Freque
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9.1A 2mW 70.7dB SNDR 200MSs Pipelined-SAR ADC with Continuous-Time SAR-Assisted
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10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differentia
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9.9 A 2.72fJconv 13b 2MSs SAR ADC Using Dynamic Capacitive Comparator with Wide
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10.5 A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using
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7.6 A 112Gbspin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss C
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7.7 A 2.16pJb 112Gbs PAM-4 Transceiver with Time-Interleaved 2b3b ADCs and Unbal
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A 42Ghz 7b 16nm Massively time-interleaved slope-ADC
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伯克利-高级模拟集成电路-EECS240-lecture2(英文字幕修正）
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10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope
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9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integra
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9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplif
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7.1 A 2.69pJb 212Gbs DSP-Based PAM-4 Transceiver for Optical Direct-Detect Appli
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10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter
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A 700MHz-BW –164dBFSHz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with
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均衡器 Equalizers 第20讲 1-Tap DFE 单泵DFE
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模拟集成电路设计9.1-二级运放的设计(理论部分）
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25届大连理工大学集成电路学院（原微电子学院）大纲分析+新招生目录分析+秋招情况+真题班导学课