Pipeline Time分析及Time Borrowing
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AXI Bus Introduction
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DFF setup_hold time分析
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Synopsys IC Compiler II Flow Introduction
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prime time 脚本使用及STA时序报告分析1
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SOC Clock Part I - Advanced SOC Design 2024
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I3C基础介绍
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part 4 _Verilog结构及例化
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DRAM 02 - DRAM vs SRAM
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IC Testing - BIST - Advanced SOC Design 2024
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SERDES 如何在 FPGA、高速串行 TX _ RX 中工作
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clock skew
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part 18 _编码器和解码器的设计 _ if else 的物理实现
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IC Testing - Boundary Scan - Advanced SOC Design 2024
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Serial RapidIO® (SRIO)简介
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part 27 _Verilog测试平台设计—文本文件的读写
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part 30 _Quartus_Synthesis综合
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part 12 _Verilog行为建模—时序电路
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part 26 _Verilog存储器建模同步FIFO
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DRAM 04 - DIMM, Rank and Channel
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Verilog基础
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FPGA/AISC Timing Optimization Background and Challenges
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FPGA/AISC Timing Optimization Optimization Strategies
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prime time 脚本使用及STA时序报告分析2
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Distributed RAM Access Timing及Blcok Ram Timing
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DRAM 05 - DDR channel上的通用读写操作
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part 6 _verilog按位操作符
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Synthesis Simulation Mismatch
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Verification Part II
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SOC design-Memory【SRAM】【DRAM】【Flash program erase】【NVM】
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SOC - Reset - Advanced SOC Design 2024
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part 11 _Verilog逻辑运算符—比较器和复用器的实现
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Verilog Tutorial ：ADC AD7819 01
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#3_ Verilog Simulation in Modelsim
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Synthesis Part I
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AXI switch Caravel Tapeout Discussion Meeting 2024
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Lab1 - FSIC-SIM Advanced SOC Design
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Y2meta.app-HLS Pipeline Part I - Advanced SOC Design 2024 03 13-(1080p)
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Part 1_Verilog HDL 特性介绍
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FPGA/AISC Timing Optimization Timer Example OLD
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FPGA/AISC Timing Optimization Timer Example