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【STA公开课】8 - 锁存器中的建立和保持时间 - Setup and Hold time inside Latch
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https://www.youtube.com/watch?v=ABx-6Aye1j8&list=PLC7JCwKQnjL6n8US3Wdt0ka7W84TJDOCK&index=8&pp=iAQB 【原作者】Team VLSI —— 搬运自youtube 【视频原标题】Setup and Hold time inside Latch 【原视频简介】The reason for Setup and Hold timing requirement inside latch has been explained in a simplified manner. To explain the topic a brief introduction about the design of latch in terms of the multiplexer, transmission gate and transistor has also been discussed. The working principle of the latch is the most important part to understand the topic. Latching edge and setup and hold timing equations also been covered in this session. The discussion flow of the session is as follow. 0:00 Introduction 1:12 Internal Structure and operation of Latch 4:35 Latching edge of the clock 6:02 Internal setup timing of the latch 9:00 Case of Setup violation 10:46 Internal hold timing of the latch -------------------------------------------------------------------- If you feel this video is relevant to your domain and useful, please like the video and subscribe to this channel. Your queries/suggestions are most welcome in the comment section. -------------------------------------------------------------------- Connect with us All links in one page: https://www.teamvlsi.com/p/contact_8.... Support Us: https://www.teamvlsi.com/p/donate-us.... Blog: https://www.teamvlsi.com Facebook Page: / teamvlsi WhatsApp Group: https://chat.whatsapp.com/C2B7VjYwCic... Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram) Email: teamvlsi2014@gmail.com
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