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7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs U
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2024ISSCC Session 7 : Ultra-High Speed Wireline
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7.4 A A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scorin
7.3 A 224Gbs 3pJb 40dB Insertion Loss Transceiver in 3nm FinFET CMOS
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm°C from -20
3.2 A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccura
10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, −253.5dB FoMJ
7.6 A 112Gbspin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss C
7.1 A 2.69pJb 212Gbs DSP-Based PAM-4 Transceiver for Optical Direct-Detect Appli
7.7 A 2.16pJb 112Gbs PAM-4 Transceiver with Time-Interleaved 2b3b ADCs and Unbal
7.2 A 224Gbs sub pJb PAM-4 and PAM-6 DAC-Based Transmitter in 3nm FinFET
10.5 A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using
3.3 A 0.5V 6.14µW Trimming-Free Single-XO Dual-Output Frequency Reference with [
3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BWPower Scalable Sensor Interface with a
ISSCC 2023 Tutorial & Short Course(RF、Power、PLL、ADC & DAC、mm-Wave、Mixer、ML)_P1_
10.6 A 10GHz FMCW Modulator Achieving 680MHzμs Chirp Slope and 150kHz rms Freque
A 12GSs 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration
3.6 An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5d
7.5 A 224Gbswire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization
9.2 A 2.08mW 64.4dB SNDR 400MSs 12b Pipelined-SAR ADC using Mismatch and PVT Var
9.4 A 182.3dB FoMs 50MSs Pipelined-SAR ADC using Cascode Capacitively Degenerate
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differentia
9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integra
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope
7.9 An 8b 6-12GHz 0.18mWGHz DC Modulated Ramp-Based Phase Interpolator in 65nm C
3.5 A 4mW 45pT√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Ca
A 76mW 40GSs 7b Time-Interleaved Hybrid VoltageTime-Domain ADC with Common-Mode
A 42Ghz 7b 16nm Massively time-interleaved slope-ADC
9.1A 2mW 70.7dB SNDR 200MSs Pipelined-SAR ADC with Continuous-Time SAR-Assisted
10.8 A 281GHz, −1.5dBm Output-Power CMOS Signal Source Adopting a 46fsrms Jitter
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS F
9.9 A 2.72fJconv 13b 2MSs SAR ADC Using Dynamic Capacitive Comparator with Wide
9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplif
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital
A 700MHz-BW –164dBFSHz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with
9.5 A 118.5dBA DR 3.3mW Audio ADC with a Class-B Resistor DAC, Non-Overlap DEM a
ISSCC 2021 Tutorial & Short Course(SC部分为PLL专题,Razavi拉扎维(UCLA)和李宇根(清华大学)
A 4.8GSs 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing
上海交通大学微电子硕士,工作5年后的薪资情况。
9.8 A 9.3nVrtHz 20b 40MSs 94.2dB DR Signal-Chain Friendly Precision SAR Converte
10.7 An 11GHz 2nd-order DPD FMCW Chirp Generator with 0.051% rms Frequency Erro
ISSCC 2023 Tutorial & Short Course(RF、Power、PLL、ADC & DAC、mm-Wave、Mixer、ML)_P5_