京东 11.11 红包
ASOC NTHU Final Project Team#1 - AES 128
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Synthesis Part III
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ASOC NTU Final Project - Lightweight Cryptographic (ASCON)
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AXI Bus Introduction
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ASOC NTHU Final Project Team#2, 3 - QPC Falcon
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ASOC NYCU Final Project - Convolution Neural Network Accelerator
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NTU Final Project - Acceleration of Attention block in Transformer
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Pipeline Time分析及Time Borrowing
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part 3 _Modelsim基础仿真
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Synopsys IC Compiler II Flow Introduction
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Step-by-Step Lab1_ FIR Part II - Advanced SOC Design 2024
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part 5 _Adder仿真及modelsim 脚本
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Lab1 - FSIC-SIM Advanced SOC Design
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Verilog模块的基本结构
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Verification Part II
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SOC - IO Part II - Advanced SOC Design
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ASOC NTHU Final Project Team#5 AES-128
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part 27 _Verilog测试平台设计—文本文件的读写
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Verification Part I
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ASOC NTU Final Project - Unet for Image Segmentation
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Caravel FSIC FPGA Simulation and Validation-(1080p)
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SOC - Power - Advanced SOC Design 2024
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Synthesis Simulation Mismatch
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Static Timing Analysis II
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JESD204 - Common Pitfalls and Traps
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Timer-DMA-GPIO介绍
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part 26 _Verilog存储器建模同步FIFO
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part 8 _assign赋值，连接，位宽匹配
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Verilog基础知识 -合集part2
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part 9 _Verilog有符号和无符号
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Lab Catapult-HLS Workbook Advanced SOC Design 2024
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part 13 _Verilog行为建模 _ 同步和异步复位
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part 25 _Verilog存储器建模ROM
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wishbone Bus
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part 18 _编码器和解码器的设计 _ if else 的物理实现
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Low Power Design - Dynamic Power Reduction - Advanced SOC Design 2024
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part 19 _Verilog定时器的设计—时钟时间的测量
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AXI switch Caravel Tapeout Discussion Meeting 2024
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DFT Compile 脚本使用及dft流程介绍
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TCL file for synthesis in genus_ design compiler
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Catapult HLS - Step-by-Step Lab FIR Part I - Advanced SOC Design 2024