5.5. Charge-sharing in dynamic gates
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6.6. Dynamic latches & registers
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3.7. Dynamic power
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5.6. Cascading in dynamic CMOS
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12.13. Sense amplifiers
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5.2. Dynamic CMOS
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5.4. Leakage in dynamic CMOS
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6.8. I_O pipelining
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3.12. Delay in CMOS gates
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3.5. CMOS capacitance and resistance
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3.3. CMOS noise margins
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5.9. Logical effort in dynamic CMOS
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3.1. CMOS inverter
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3.2. CMOS VTC
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1.1. Classical model of silicon
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6.5. Imperfect clocks and hold time
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3.4. Preliminaries of CMOS delay
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3.10. Complex CMOS gates
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5.3. Delay in dynamic CMOS
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2.1. PMOS Transistors
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3.6. CMOS delay model
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12.12. SRAM read and write
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7.8. Etching & CMP
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2.2. Preliminaries of logic
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5.7. NP logic
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2.5. Bipolar logic
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2.7. Enhancement load inverter
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1.12. PN junction
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1.5. Intrinsic silicon
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6.1. Sequential CMOS
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4.8. Complications of optimization
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4.1. Sizing in a chain
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6.9. Internal pipelining
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5.1. High impedance nodes
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12 21 Row decoders design using logical effort
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7.9. Exposure strategies
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1.11. Diffusion
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7.7. Photoresist coating, baking, & development
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2.11. Complex enhancement synthesis
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4.7. Analyzing optimal solutions
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2.8. Enhancement load VTC