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2.2. Preliminaries of logic
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Preliminaries of logic
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4.6. Optimizing logic
5.7. NP logic
4.5. Logical effort
5.8. Domino logic
2.5. Bipolar logic
6.8. I_O pipelining
3.4. Preliminaries of CMOS delay
2.4. Characterization of logic
4.3. Chain of random logic
4.4. Parasitic delay
1.4. Carrier concentration
12.11. SRAM cell
12.12. SRAM read and write
12.13. Sense amplifiers
1.6. Doping
6.5. Imperfect clocks and hold time
7.8. Etching & CMP
6.9. Internal pipelining
4.8. Complications of optimization
7.9. Exposure strategies
2.1. PMOS Transistors
6.6. Dynamic latches & registers
7.7. Photoresist coating, baking, & development
6.2. CMOS latches
4.2. Inverter chains
7.4. Czochralsky process and wafer preparation
7.2. Photolithography
1.12. PN junction
7.10. Alignment
6.1. Sequential CMOS
4.7. Analyzing optimal solutions
6.7. Basics of pipelining
6.10. Setup-time violations
7.6. CVD, PVD, & oxidation
12.18. Column decoders
2.7. Enhancement load inverter
12 21 Row decoders design using logical effort
6.12. I_O alignment in pipelines
6.3. CMOS registers
2.6. RTL