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5.1. High impedance nodes
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high impedance nodes
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12.9. NOR FLASH
12.13. Sense amplifiers
1.6. Doping
6.8. I_O pipelining
12.11. SRAM cell
12.12. SRAM read and write
7.2. Photolithography
7.10. Alignment
6.5. Imperfect clocks and hold time
4.2. Inverter chains
6.6. Dynamic latches & registers
1.4. Carrier concentration
6.9. Internal pipelining
7.8. Etching & CMP
4.8. Complications of optimization
6.10. Setup-time violations
4.6. Optimizing logic
4.4. Parasitic delay
7.9. Exposure strategies
12.10. NAND FLASH
2.3. Scaling MOSFET
1.11. Diffusion
Lecture 15_ Booting Process
1.9. Drift
4.1. Sizing in a chain
2.5. Bipolar logic
1.12. PN junction
6.7. Basics of pipelining
7.7. Photoresist coating, baking, & development
1.2. Band model
1.8. Mass action law
12.2. Memory array architecture
7.11. LOCOS part 1
4.7. Analyzing optimal solutions
1.7. Extrinsic silicon
7.12. LOCOS part 2
7.3. Account of materials
3.7. Dynamic power
2.8. Enhancement load VTC
12 21 Row decoders design using logical effort