6.9. Internal pipelining
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6.8. I_O pipelining
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6.7. Basics of pipelining
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12.11. SRAM cell
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12.12. SRAM read and write
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12.9. NOR FLASH
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4.8. Complications of optimization
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7.9. Exposure strategies
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12.13. Sense amplifiers
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1.6. Doping
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7.8. Etching & CMP
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4.4. Parasitic delay
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4.6. Optimizing logic
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4.5. Logical effort
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1.4. Carrier concentration
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7.7. Photoresist coating, baking, & development
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4.2. Inverter chains
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7.4. Czochralsky process and wafer preparation
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6.6. Dynamic latches & registers
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2.2. Preliminaries of logic
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2.1. PMOS Transistors
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1.5. Intrinsic silicon
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5.7. NP logic
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6.5. Imperfect clocks and hold time
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6.1. Sequential CMOS
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7.2. Photolithography
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2.5. Bipolar logic
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1.7. Extrinsic silicon
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4.7. Analyzing optimal solutions
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7.1. CMOS fabrication facilities
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12 21 Row decoders design using logical effort
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2.7. Enhancement load inverter
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4.1. Sizing in a chain
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3.7. Dynamic power
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6.12. I_O alignment in pipelines
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7.10. Alignment
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5.5. Charge-sharing in dynamic gates
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6.2. CMOS latches
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1.12. PN junction
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2.3. Scaling MOSFET
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7.6. CVD, PVD, & oxidation