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6.6. Dynamic latches & registers
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Dynamic latches & registers
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6.3. CMOS registers
5.5. Charge-sharing in dynamic gates
5.6. Cascading in dynamic CMOS
3.7. Dynamic power
5.9. Logical effort in dynamic CMOS
6.2. CMOS latches
5.4. Leakage in dynamic CMOS
6.8. I_O pipelining
12.11. SRAM cell
12.13. Sense amplifiers
4.8. Complications of optimization
6.9. Internal pipelining
4.4. Parasitic delay
4.5. Logical effort
2.1. PMOS Transistors
7.9. Exposure strategies
12.12. SRAM read and write
7.8. Etching & CMP
1.3. Metals, insulators, & semiconductors
5.3. Delay in dynamic CMOS
1.4. Carrier concentration
6.5. Imperfect clocks and hold time
1.10. Silicon conductivity
4.2. Inverter chains
7.4. Czochralsky process and wafer preparation
4.7. Analyzing optimal solutions
5.2. Dynamic CMOS
7.7. Photoresist coating, baking, & development
6.7. Basics of pipelining
2.11. Complex enhancement synthesis
1.6. Doping
2.2. Preliminaries of logic
2.9. Enhancement load NOR
2.7. Enhancement load inverter
2.3. Scaling MOSFET
6.1. Sequential CMOS
7.6. CVD, PVD, & oxidation
4.6. Optimizing logic
1.5. Intrinsic silicon
12.4. Delay in NOR ROM