6.6. Dynamic latches & registers
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6.3. CMOS registers
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5.5. Charge-sharing in dynamic gates
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5.6. Cascading in dynamic CMOS
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3.7. Dynamic power
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5.9. Logical effort in dynamic CMOS
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6.2. CMOS latches
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5.4. Leakage in dynamic CMOS
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6.8. I_O pipelining
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12.11. SRAM cell
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12.13. Sense amplifiers
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4.8. Complications of optimization
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6.9. Internal pipelining
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4.4. Parasitic delay
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4.5. Logical effort
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2.1. PMOS Transistors
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7.9. Exposure strategies
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12.12. SRAM read and write
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7.8. Etching & CMP
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1.3. Metals, insulators, & semiconductors
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5.3. Delay in dynamic CMOS
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1.4. Carrier concentration
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6.5. Imperfect clocks and hold time
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1.10. Silicon conductivity
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4.2. Inverter chains
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7.4. Czochralsky process and wafer preparation
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4.7. Analyzing optimal solutions
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5.2. Dynamic CMOS
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7.7. Photoresist coating, baking, & development
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6.7. Basics of pipelining
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2.11. Complex enhancement synthesis
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1.6. Doping
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2.2. Preliminaries of logic
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2.9. Enhancement load NOR
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2.7. Enhancement load inverter
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2.3. Scaling MOSFET
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6.1. Sequential CMOS
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7.6. CVD, PVD, & oxidation
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4.6. Optimizing logic
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1.5. Intrinsic silicon
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12.4. Delay in NOR ROM