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4.6. Optimizing logic
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2.2. Preliminaries of logic
4.5. Logical effort
2.5. Bipolar logic
5.7. NP logic
5.8. Domino logic
6.8. I_O pipelining
2.4. Characterization of logic
12.9. NOR FLASH
4.3. Chain of random logic
6.9. Internal pipelining
4.8. Complications of optimization
2.1. PMOS Transistors
1.6. Doping
12.13. Sense amplifiers
12.12. SRAM read and write
1.4. Carrier concentration
7.9. Exposure strategies
4.4. Parasitic delay
7.7. Photoresist coating, baking, & development
12.11. SRAM cell
12.18. Column decoders
7.8. Etching & CMP
2.9. Enhancement load NOR
7.4. Czochralsky process and wafer preparation
1.5. Intrinsic silicon
6.6. Dynamic latches & registers
6.7. Basics of pipelining
4.2. Inverter chains
12.15. Three transistor DRAM
6.5. Imperfect clocks and hold time
12 21 Row decoders design using logical effort
2.7. Enhancement load inverter
1.7. Extrinsic silicon
2.3. Scaling MOSFET
7.1. CMOS fabrication facilities
12.16. One transistor DRAM
7.6. CVD, PVD, & oxidation
3.7. Dynamic power
6.1. Sequential CMOS
4.7. Analyzing optimal solutions