1.6. Doping
发布人
打开封面 下载高清视频 观看高清视频 视频下载器
...
7.5. Ion implantation & diffusion
...
12.9. NOR FLASH
...
12.13. Sense amplifiers
...
12.11. SRAM cell
...
6.8. I_O pipelining
...
6.5. Imperfect clocks and hold time
...
1.5. Intrinsic silicon
...
6.2. CMOS latches
...
2.9. Enhancement load NOR
...
7.8. Etching & CMP
...
1.7. Extrinsic silicon
...
6.9. Internal pipelining
...
12.10. NAND FLASH
...
1.9. Drift
...
2.2. Preliminaries of logic
...
7.10. Alignment
...
2.7. Enhancement load inverter
...
4.4. Parasitic delay
...
5.2. Dynamic CMOS
...
2.1. PMOS Transistors
...
12.8. EPROM & EEPROM
...
6.1. Sequential CMOS
...
6.3. CMOS registers
...
6.12. I_O alignment in pipelines
...
4.6. Optimizing logic
...
12.12. SRAM read and write
...
6.7. Basics of pipelining
...
4.8. Complications of optimization
...
4.2. Inverter chains
...
1.2. Band model
...
4.1. Sizing in a chain
...
Android Boot Process
...
7.12. LOCOS part 2
...
7.9. Exposure strategies
...
5.4. Leakage in dynamic CMOS
...
1.11. Diffusion
...
7.11. LOCOS part 1
...
1.4. Carrier concentration
...
6.10. Setup-time violations
...
2.11. Complex enhancement synthesis