6.10. Setup-time violations
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6.4. Setup time and CQ delay
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12.13. Sense amplifiers
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6.11. Hold-time violations
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6.5. Imperfect clocks and hold time
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7.10. Alignment
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1.3. Metals, insulators, & semiconductors
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12.2. Memory array architecture
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6.9. Internal pipelining
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2.10. Enhancement NAND gate
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7.9. Exposure strategies
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6.8. I_O pipelining
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4.2. Inverter chains
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4.8. Complications of optimization
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1.4. Carrier concentration
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12.1. Memories motivation & classification
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2.7. Enhancement load inverter
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12.20. Row decoders
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12.4. Delay in NOR ROM
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1.6. Doping
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7.3. Account of materials
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2.3. Scaling MOSFET
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1.12. PN junction
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12.11. SRAM cell
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7.7. Photoresist coating, baking, & development
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7.2. Photolithography
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7.4. Czochralsky process and wafer preparation
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12 21 Row decoders design using logical effort
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12.15. Three transistor DRAM
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4.6. Optimizing logic
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6.1. Sequential CMOS
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2.11. Complex enhancement synthesis
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2.8. Enhancement load VTC
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5.8. Domino logic
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6.3. CMOS registers
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6.7. Basics of pipelining
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5.4. Leakage in dynamic CMOS
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7.11. LOCOS part 1
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1.5. Intrinsic silicon
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4.7. Analyzing optimal solutions
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12.7. Non volatile memories