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7.11. LOCOS part 1
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7.12. LOCOS part 2
12.11. SRAM cell
12.9. NOR FLASH
2.11. Complex enhancement synthesis
12.13. Sense amplifiers
12.8. EPROM & EEPROM
6.8. I_O pipelining
1.11. Diffusion
1.6. Doping
7.10. Alignment
12.10. NAND FLASH
12.7. Non volatile memories
7.2. Photolithography
1.9. Drift
12.12. SRAM read and write
12.4. Delay in NOR ROM
1.3. Metals, insulators, & semiconductors
1.10. Silicon conductivity
12.2. Memory array architecture
12.1. Memories motivation & classification
1.2. Band model
1.8. Mass action law
6.5. Imperfect clocks and hold time
4.2. Inverter chains
7.3. Account of materials
1.7. Extrinsic silicon
1.12. PN junction
5.2. Dynamic CMOS
7.8. Etching & CMP
2.3. Scaling MOSFET
1.5. Intrinsic silicon
4.5. Logical effort
6.9. Internal pipelining
3.7. Dynamic power
4.4. Parasitic delay
7.9. Exposure strategies
1.4. Carrier concentration
2.1. PMOS Transistors
2.5. Bipolar logic
6.10. Setup-time violations