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12.16. One transistor DRAM
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12.9. NOR FLASH
12.11. SRAM cell
12.15. Three transistor DRAM
12.13. Sense amplifiers
12.17. DRAM read, write, and refresh cycles
12.8. EPROM & EEPROM
12.10. NAND FLASH
12 21 Row decoders design using logical effort
12.12. SRAM read and write
6.8. I_O pipelining
12.1. Memories motivation & classification
6.12. I_O alignment in pipelines
12.2. Memory array architecture
1.4. Carrier concentration
1.6. Doping
4.4. Parasitic delay
6.9. Internal pipelining
2.12. Complex enhancement analysis
4.5. Logical effort
2.1. PMOS Transistors
12.7. Non volatile memories
12.20. Row decoders
7.9. Exposure strategies
7.12. LOCOS part 2
6.5. Imperfect clocks and hold time
7.8. Etching & CMP
4.8. Complications of optimization
12.6. Delay in NAND ROM
7.2. Photolithography
7.10. Alignment
4.2. Inverter chains
2.7. Enhancement load inverter
6.6. Dynamic latches & registers
7.7. Photoresist coating, baking, & development
7.4. Czochralsky process and wafer preparation
6.7. Basics of pipelining
1.8. Mass action law
1.11. Diffusion
5.5. Charge-sharing in dynamic gates
2.3. Scaling MOSFET