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12.9. NOR FLASH
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12.13. Sense amplifiers
12.10. NAND FLASH
12.11. SRAM cell
12.3. NOR ROM
3.9. CMOS NAND and NOR
12.4. Delay in NOR ROM
7.12. LOCOS part 2
1.6. Doping
6.12. I_O alignment in pipelines
12.12. SRAM read and write
2.9. Enhancement load NOR
12.20. Row decoders
12.17. DRAM read, write, and refresh cycles
12.15. Three transistor DRAM
6.8. I_O pipelining
12.8. EPROM & EEPROM
12.6. Delay in NAND ROM
1.9. Drift
4.2. Inverter chains
7.10. Alignment
7.8. Etching & CMP
12.16. One transistor DRAM
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2.3. Scaling MOSFET
6.9. Internal pipelining
5.1. High impedance nodes
7.11. LOCOS part 1
5.7. NP logic
1.8. Mass action law
2.8. Enhancement load VTC
1.5. Intrinsic silicon
6.4. Setup time and CQ delay
1.12. PN junction
2.5. Bipolar logic
2.6. RTL
2.1. PMOS Transistors
4.6. Optimizing logic
Introduction to Memory Management in Linux
2.10. Enhancement NAND gate
12.5. NAND ROM