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7.12. LOCOS part 2
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12.9. NOR FLASH
7.11. LOCOS part 1
12.11. SRAM cell
12.12. SRAM read and write
12.13. Sense amplifiers
12.7. Non volatile memories
6.12. I_O alignment in pipelines
12.8. EPROM & EEPROM
12.10. NAND FLASH
12.20. Row decoders
12.17. DRAM read, write, and refresh cycles
12.15. Three transistor DRAM
12.2. Memory array architecture
12.6. Delay in NAND ROM
2.12. Complex enhancement analysis
12.3. NOR ROM
7.8. Etching & CMP
1.6. Doping
12.16. One transistor DRAM
4.4. Parasitic delay
12.4. Delay in NOR ROM
7.10. Alignment
6.8. I_O pipelining
1.12. PN junction
2.2. Preliminaries of logic
4.6. Optimizing logic
1.4. Carrier concentration
6.9. Internal pipelining
2.11. Complex enhancement synthesis
1.3. Metals, insulators, & semiconductors
7.2. Photolithography
7.6. CVD, PVD, & oxidation
7.7. Photoresist coating, baking, & development
1.11. Diffusion
2.1. PMOS Transistors
2.5. Bipolar logic
12.5. NAND ROM
4.8. Complications of optimization
6.10. Setup-time violations
7.9. Exposure strategies